As the speed and bandwidth of integrated circuit interconnects have increased in recent years—particularly those interconnects used in conjunction with Application Specific Integrated Circuits (ASICs)—there has been an increased interest in the use of source-synchronous interconnects. In general, a source-synchronous interconnect is one in which data and clock signals are sent from a source to a responder, and the clock signal is then used within the responder interface to latch the accompanying data. Such source-synchronous interconnects are known to exhibit improved tolerance to process-voltage-temperature (PVT) variations.
Conventional source-synchronous interconnects are unsatisfactory in a number of respects, however. For example, many source-synchronous interconnect schemes are susceptible to non-determinism resulting from, among other things, clock insertion differences between the source and the responder. Such non-determinism can complicate system validation processes such as post-silicon debugging and at-speed testing.
Accordingly, there is a need for systems and methods that can eliminate or reduce non-determinism in source-synchronous circuits and interfaces.